Semiconductor structure and manufacturing method thereof

ABSTRACT

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority to U.S. patent application Ser. No. 62/273,461 filed 2015 Dec. 31, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Electronic equipment involving semiconductive devices are essential for many modem applications. Technological advances in materials and designs have produced generations of semiconductive devices where each generation has smaller and more complex circuits than the previous generation. In the course of advancement and innovation, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased. Such advances have increased the complexity of processing and manufacturing semiconductive devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a schematic view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 1B is a schematic view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 1C is a schematic view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 2A-2Q are schematic views of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure is directed to a semiconductor structure with an improved bond pad design. The bond pad is composed of materials with greater resistance to stress, such as pull stress or shear stress, during the manufacturing or packaging of the semiconductor structure. In addition, the semiconductor structure exhibits better bonding properties. Thus, the risk of structure cracking or peeling is effectively mitigated.

FIG. 1A is a schematic view of a semiconductor structure 100, in accordance with some embodiments of the present disclosure. The semiconductor structure 100 comprises a first semiconductor device 110 and a second semiconductor device 120. The first semiconductor device 110 comprises a first semiconductive substrate 112 and a first interconnect structure 114. The second semiconductor device 120 comprises a second semiconductive substrate 122 and a second interconnect structure 124.

The second semiconductor device 120 is configured to perform specific functions and communicate with the first semiconductor device 110. In some embodiments, the second semiconductor device 120 may include a logic circuit. In some embodiments, the second semiconductor device 120 may further include memory cells or other electrical components. In some embodiments, the second semiconductive substrate 122 may include a myriad of passive or active components (not shown) disposed on a surface 122A facing the second interconnect structure 124.

The second semiconductive substrate 122 includes a semiconductor material such as silicon. In some embodiments, the second semiconductive substrate 122 may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In some embodiments, the second semiconductive substrate 122 is a p-type semiconductive substrate (acceptor type) or n-type semiconductive substrate (donor type). Alternatively, the second semiconductive substrate 122 includes another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonids; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the second semiconductive substrate 122 is a semiconductor-on-insulator (SOI). In other alternatives, the second semiconductive substrate 122 may include a doped epi layer, a gradient semiconductor layer, and/or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer.

The second interconnect structure 124 is disposed over the second semiconductive substrate 122. In some embodiments, the second interconnect structure 124 is disposed between the first interconnect structure 114 and the second semiconductive substrate 122. The second interconnect structure 124 is configured to electrically couple electrical components within the second semiconductive substrate 122. In some embodiments, the second interconnect structure 124 is configured to electrically couple the second semiconductive substrate 122 with a device or component external to the second semiconductor device 120. In the present embodiment, the second interconnect structure 124 electrically couples the second semiconductive substrate 122 with the first interconnect structure 114 of the first semiconductor device 110. The second interconnect structure 124 may include multiple metal layers. Each of the metal layers may include conductive wires or lines and is electrically coupled to an adjacent overlaying or underlying metal layer through at least one metal via. In the present embodiment, metal layers 131, 133, 135 and 137 are disposed in a layered structure and are interconnected through corresponding metal vias 132, 134 and 136. The numbers and patterns of the metal layers and vias of the second interconnect structure 124 are provided for illustration. Other numbers of metal layers, metal vias, or conductive wires and alternative wiring patterns are also within the contemplated scope of the present disclosure.

Moreover, the aforesaid metal layers and metal vias are electrically insulated from other components. The insulation may be achieved by insulating materials. In some embodiments, the remaining portion of the second interconnect structure 124 may be filled with an inter-metal dielectric (IMD) 123. The dielectric material of IMD 123 may be formed of oxides, such as un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials may have k values lower than 3.8, although the dielectric materials of the IMD 123 may also be close to 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5.

The first semiconductor device 110 is configured to perform specific functions and communicate with the second semiconductor device 120. In some embodiments, the first semiconductor device 110 may be a sensing device, for example, a backside image (BSI) sensor device configured to capture image data. In some embodiments, the first semiconductive substrate 112 may include a myriad of passive or active components (not shown) disposed on a surface 112B facing the first interconnect structure 114.

The first interconnect structure 114 is disposed against the first semiconductive substrate 112. In some embodiments, the first interconnect structure 114 is disposed between the second interconnect structure 124 and the first semiconductive substrate 112. In some embodiments, the first interconnect structure 114 is configured to electrically couple the components of the first semiconductive substrate 112 with a device or component external to the first semiconductor device 110. In the present embodiment, the first interconnect structure 114 electrically couples the first semiconductive substrate 112 with the second interconnect structure 124 of the second semiconductor device 120. The first interconnect structure 114 may include multiple metal layers. Each of the metal layers includes at least one conductive line and is electrically coupled to an adjacent metal layer through at least one metal via. In the present embodiment, metal layers 141, 143, 145 and 147 are disposed in the second interconnect structure 114 and are interconnected through metal vias 142, 144 and 146.

In some embodiments, the remaining portion of the interconnect structure 114 may be filled with an IMD 113. The dielectric material for the IMD 113 may be formed of oxides, such as un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials may have k values lower than 3.8, although the dielectric materials of the IMD 113 may be also close to 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5.

In some embodiments, the first interconnect structure 114 further comprises several bond pads 154 on a surface 114A facing the second interconnect structure 124. In some embodiments, the second interconnect structure 124 comprises several bond pads 152 on a surface 124A facing the first interconnect structure 114. The bond pads 154 are aligned with corresponding bond pads 152 such that the first semiconductor device 110 and the second semiconductor device 120 are electrically bonded. In some embodiments, the bond pads 154 and 152 may protrude from the surface 114A and 124A, respectively. In some embodiments, the bond pads 152 are planar with the surface 114A. In some embodiments, the bond pads 154 are planar with the surface 124A. In some embodiments, the bond pads 152 and 154 are planar with the surface 114A and 124A, respectively, such that the surface 114A is in contact with the surface 124A.

The first semiconductive substrate 112 is disposed above the first interconnect structure 114. The first semiconductive substrate 112 may include silicon, silicon germanium, silicon carbide, gallium arsenide, and/or germanium. Alternatively, the first semiconductive substrate 112 may include a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonids; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some embodiments, the first semiconductive substrate 112 may be formed of materials similar to the second semiconductive substrate 122. In some embodiments, the first semiconductive substrate 112 may include materials different from the second semiconductive substrate 122.

In some embodiments, the first semiconductor device 110 may include a dielectric layer 162 between the semiconductive substrate 112 and the second interconnect structure 114. In some embodiments, the first semiconductor device 110 may include a dielectric layer 164 external but against the semiconductive substrate 112. The dielectric layer 162 and dielectric layer 164 are respectively disposed on opposite sides of the semiconductive substrate 112. The dielectrics 162 and 164 may include a variety of dielectric materials and may, for example, be an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO₂), a nitrogen-bearing oxide (e.g., nitrogen-bearing SiO₂), a nitrogen-doped oxide (e.g., N₂-implanted SiO₂), silicon oxynitride (Si_(x)O_(y)N_(z)), and the like. In some embodiments, the dielectric 162 is formed of the same materials as that of the dielectric 164. In some embodiments, the dielectric 162 is formed of different materials from that of the dielectric 164.

In some embodiments, the first semiconductive substrate 112 includes a first via 160. The first via 160 comprises a terminal 168 and a dielectric 166. In some embodiments, the dielectric 166 surrounds the terminal 168 in a lateral direction substantially parallel to a top surface 112A of the first semiconductive substrate 112. In some embodiments, the dielectric 166 includes multiple dielectric materials. Alternatively, the dielectric 166 includes a multi-layer structure. The terminal 168 is extended through the semiconductive substrate 112 and configured to electrically couple the first interconnect structure 114 with an external component through a connector 172. In some embodiments, the dielectric 166 in the first via 160 includes a second via 160′. The terminal 168 is disposed in the second via 160′. The dielectric 166 surrounds the second via 160′ in a lateral direction substantially parallel to a top surface 112A of the first semiconductor substrate 112. In some embodiments, the terminal 168 electrically connects the connector 172 with the metal layer 141 of the first interconnect structure 114. In some embodiments, the connector 172 is a wire bond or a solder bump.

In some embodiments, the semiconductor structure 100 may include an under bump metallurgy (UBM) 174 between the first via 160 and the connector 172. The UBM 174 is configured to provide better adhesion of the connector 172. In some embodiments, the UBM 174 covers the first via 160. In some embodiments, the UBM 174 includes a top surface higher than a top surface of the dielectric layer 164.

FIG. 1B is an enlarged schematic view of a portion of the semiconductor structure 100 in FIG. 1A, in accordance with some embodiments of the present disclosure. Specifically, the first semiconductor device 110 is illustrated with more details. In some embodiments, the first semiconductive substrate 112 further comprises a dielectric 167. In some embodiments, the dielectric 167 is in the first via 160 and lining along sidewalls of the first via 160. In some embodiments, the dielectric 167 surrounds the dielectric 166 and the terminal 168 from a lateral direction substantially parallel to the top surface 112A of the first semiconductor substrate 112. Referring to FIG. 1B, the dielectric 167 surrounds a lateral side and a bottom side of the dielectric 166.

In some embodiments, the first semiconductive substrate 112 further comprises a dielectric 165. A portion of the dielectric 165 is in the first via 160. The dielectric 165 is disposed between the dielectric 162 and the bottom side of the dielectric 167. In some embodiments, the dielectric 165 has a top surface which includes an area larger than the cross-sectional area of the first via 160. In the present embodiments, the terminal 168 is electrically connected with the metal layer 141 and passes through the dielectrics 166, 167, 162 and 165. In other words, the terminal 168 is surrounded by the dielectrics 166, 167, 162 and 165 in a lateral direction substantially parallel to the top surface 112A.

In some embodiments, the metal layer 141 includes conductive materials such as gold, silver and tungsten. The metal layer 141 includes a thickness T measured from a direction perpendicular to the surface 112A. In some embodiments, the thickness T is from about 500 Å to about 3000 Å. In some embodiments, the thickness T is from about 1000 Å to about 3000 Å. In some embodiments, the thickness T is from about 1000 Å to about 2000 Å.

The terminal 168 is illustrated with shading in FIG. 1A. The terminal 168 is also illustrated with shading in FIG. 1B in a similar shape although not specifically labeled. In some embodiments, the terminal 168 serves as a conductive plug electrically coupling the connector 172 with the first interconnect structure 114. In some embodiments, the terminal 168 may be a bond pad. The bond pad 168 has a height H measured from a bottom surface 168B to a top surface 168A. In some embodiments, the height H may be from about 16,000 Å to about 35,000 Å. In some embodiments, the height H may be from about 20,000 Å to about 30,000 Å. In some embodiments, the height H may be from about 24,000 Å to about 28,000 Å.

The dielectric 166 has a top surface 166A. In some embodiments, the top surface 166A has a flat shape. In some embodiments, the top surface 166A has a curved shape such as a concave surface. In the present embodiments, the top surface 166A has an upwardly concave surface. The curved shape of the top surface 166A may be due to a dishing effect of a planarization process, such as the chemical mechanical polishing (CMP) operation.

In some embodiments, the dielectric 167 includes a top surface 167A. In some embodiments, the top surface 167A includes a flat shape. In some embodiments, the top surface 167A includes a curved shape such as a concave shape. For example, the top surface 167A may include an upwardly concave shape.

In some embodiments, the top surface 168A has a flat shape. In some embodiments, the top surface 168A has a curved shape. In some embodiments, the top surface 168A has a concave shape, such as a downwardly concave shape.

in some embodiments, the bond pad 168 has a sidewall 168C interfacing with the dielectric 166. The bond pad 168 has a top width W1 measured along a top level of the sidewall 168C and a bottom width W2 measured along the bottom surface 168B. In some embodiments, the top width W1 is larger than the bottom width W2. In some embodiments, the bond pad 168 includes a tapered shape from the top surface 168A to the bottom surface 168B.

In some embodiments, the top surface 168A is lower than the top surface 166A of the dielectric 166. In some embodiments, the top surface 168A meets with the top surface 166A of the dielectric 166. In some embodiments, the top surface 168A is lower than the top surface 112A of the dielectric 164. In some embodiments, the top surface 168A is substantially coplanar or leveled with the top surface 112A of the dielectric 164. In some embodiments, the top surface 168A is lower than a top surface 167A of the dielectric 167.

The bond pad 168 electrically couples to the metal layer 141 at the bottom surface 168B. In some embodiments, the bond pad 168 couples to the metal layer 141 via the single contact 168B. In some embodiments, the bond pad 168 comprises a flat bottom surface 16813 in contact with the metal layer 141.

The bond pad 168 comprises at least two layers. In the present embodiment, the bond pad 168 (illustrated with shading while not labeled in FIG. 1B) comprises a first layer 169 and a second layer 170. The first layer 169 is coupled to the metal layer 141 of the first interconnect structure 114. In some embodiments, the first layer 169 includes a tapered shape from a cross-sectional view. In some embodiments, the first layer 169 may include a conductive material with Young's modulus from about 150 gigapascals (GPa) to about 250 GPa. In some embodiments, the first layer 169 may include a conductive material with Young's modulus from about 180 GPa to about 220 GPa. In some embodiments, the first layer 169 may include a conductive material with Young's modulus from about 190 GPa to about 210 GPa. In some embodiments, the first layer 169 may include metal such as gold, silver, copper, tungsten or nickel.

In some embodiments, the first layer 169 may include a conductive material with a weight percentage concentration from about 85% to about 100%. In some embodiments, the first layer 169 may include a conductive material with a weight percentage concentration from about 90% to about 100%. In some embodiments, the first layer 169 may include a conductive material with a weight percentage concentration from about 93% to about 95%. In some embodiments, the conductive material of the first layer 169 includes gold, silver, copper, tungsten or nickel.

The first layer 169 includes a height H1 measured from the bottom surface 168B to an upper surface 169A. In some embodiments, the height H1 is from about 15,000 Å to about 30,000 Å. In some embodiments, the height H1 is from about 15,000 Å to about 25,000 Å. In some embodiments, the height H1 is from about 20,000 Å to about 25,000 Å.

The second layer 170 electrically connects the first layer 169 with the UBM 174. In some embodiments, the second layer 170 is exposed from the dielectric 166. The second layer 170 has a top surface which is the top surface of the bond pad 168 and labeled as 168A. In some embodiments, the top surface 168A of the second layer 170 meets with the top surface 166A of the dielectric 166. In some embodiments, the top surface 168A is lower than the top surface 166A of the dielectric 166. In some embodiments, the second layer 170 includes a quadrilateral shape. In some embodiments, the second layer 170 includes a trapezoidal shape.

In some embodiments, the top surface 168A of the second layer 170 has a flat shape. In some embodiments, the top surface 168A of the second layer has a curved shape. In some embodiments, the top surface 168A of the second layer has a concave shape, such as a downwardly concave shape.

In some embodiments, the second layer 170 may include a conductive material with Young's modulus from about 50 GPa to about 120 GPa. In some embodiments, the second layer 170 may include a conductive material with Young's modulus from about 60 GPa to about 100 GPa. In some embodiments, the second layer 170 may include a conductive material with Young's modulus from about 70 GPa to about 80 GPa. In some embodiments, the second layer 170 may include metal such as gold, silver, copper, tungsten or nickel.

In some embodiments, the second layer 170 may include a conductive material with a weight percentage concentration from about 95% to about 100%. In some embodiments, the second layer 170 may include a conductive material with a weight percentage concentration from about 99% to about 100%. In some embodiments, the second layer 170 may include metal such as gold, silver, copper, tungsten or nickel.

The second layer 170 includes a height H2 measured from the surface 169A to the upper surface 168A. In the embodiments, the height H2 is from about 500 Å to about 3000 Å. In the embodiments, the height H2 is from about 1000 Å to about 3000 Å. In the embodiments, the height H2 is from about 1000 Å to about 2000 Å.

In some embodiments, a ratio of Young's modulus between the first layer 169 and the second layer 170 is from about 1.5 to about 3.5. In some embodiments, a ratio of Young's modulus between the first layer 169 and the second layer 170 is from about 2.0 to about 3.0. In some embodiments, a ratio of Young's modulus between the first layer 169 and the second layer 170 is from about 2.4 to about 2.6.

FIG. 1C is an enlarged schematic view of a portion of the semiconductor structure 100 in FIG. 1A, in accordance with some embodiments of the present disclosure. Specifically, the first semiconductor device 110 is illustrated with more details. Referring to FIG. 1C, the top surface 168A is higher than the top surface 166A of the dielectric 166. In some embodiments, the top surface 168A is higher than the top surface 112A of the dielectric 164. In some embodiments, the top surface 168A is higher than the top surface 167A of the dielectric 167. In some embodiments, a portion of the bond pad 168 covers a portion of the dielectric 166. In some embodiments, a cap portion of the bond pad 168 extends over the dielectric 166. In some embodiments, the cap portion of the bond pad 168 extends along a direction parallel to the top surface 112A of the first semiconductive substrate 112. In some embodiments, the dielectric 166 is covered partially by the UBM 174 and partially by the bond pad 168.

In some embodiments, the second layer 170 covers a portion of the top surface 166A of the dielectric 166. In some embodiments, the second layer 170 extends over the dielectric 166. In some embodiments, the top surface 168A of the second layer 170 has a flat shape. In some embodiments, the top surface 168A of the second layer 170 has a curved shape, such as a concaved shape. In some embodiments, the upper surface 169A meets with a top level of the sidewall 168C such that the second layer 170 is higher than the top surface 166A of the dielectric 166. In some embodiments, the cap portion of the second layer 170 includes a quadrilateral shape. In some embodiments, the cap portion of the second layer 170 includes a trapezoidal shape. In some embodiments, the cap portion of the second layer 170 covers a portion of the dielectric 166.

FIG. 2A to FIG. 2Q show cross-sectional views of the semiconductor structure 100 of FIG. 1A fabricated at various stages, in accordance with some embodiments of the present disclosure. In FIG. 2A, the first semiconductive substrate 112 is provided. In some embodiments, at least one structure of a sensing device (not shown) may be formed in the first semiconductive substrate 112. The first semiconductive substrate 112 has a first dopant type, such as a P-type.

In some embodiments, a dielectric 162 is blanket deposited at a topmost level of the first semiconductive substrate 112. The dielectric 162 may be formed by vapor deposition or spin coating. “Vapor deposition” refers to processes of depositing materials on a substrate though the vapor phase. Vapor deposition processes include any process such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). Examples of vapor deposition methods include hot filament CVD, radio-frequency CVD (rf-CVD), laser CVD (LCVD), conformal diamond coating processes, metal-organic CVD (MOCVD), sputtering, thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), low-pressure CVD (LPCVD) and the like. In some embodiments, the dielectric 162 includes silicon oxide or silicon nitride. In some embodiments, the upper most level dielectric 162 is also configured as a passivation layer.

Referring to FIG. 2B, the first interconnect structure 114 is formed over the first semiconductive substrate 112. The first interconnect structure 114 may be formed of stacked metal layers from a bottom layer to a top layer. For example, the metal layer 147 is formed by depositing a mask layer (not separately shown) on the first semiconductive substrate 112. The mask layer is patterned through an etching operation to form desired patterns for the metal layer 141. Then, conductive materials are filled in the etched patterns. The mask layer is striped by a removing operation after the pattern is filled with conductive materials. The IMD material 113 may be filled among the conductive materials of the metal layer 141. Similarly, the conductive via layer 142 is formed over the metal layer 141 in order to generate a conductive connection between the metal layer 141 and the overlaying metal layer 142. The metal layers 143, 145 and 147 are formed in sequence along with the intervening conductive via layers 144 and 146. A portion of the metal layer 147 is exposed from the first interconnect structure 114,

Referring to FIG. 2C, several bond pads 154 are formed at a topmost level of the first interconnect structure 114. In some embodiments, each of the bond pads 154 has a top surface 154A higher than a top surface 113A of the IMD 113. In some embodiments (not shown), the top surface 113A may be configured to level with the top surface 154A such that the first interconnect structure 114 has a planarized top surface 114A of FIG. 1A. The first semiconductive substrate 112 and the first interconnect structure 114 constitutes the first semiconductor device 110.

FIGS. 2D-2F show cross-sectional views of the second semiconductor device 120 fabricated at various stages, in accordance with some embodiments of the present disclosure. The second semiconductive substrate 122 is provided as shown in FIG. 2D. In some embodiments, at least one active or passive structure (not shown) may be formed in the first semiconductive substrate 122. The first semiconductive substrate 122 has a first dopant type, such as a P-type.

Referring to FIG. 2E, the second interconnect structure 124 is formed over the second semiconductive substrate 122. The second interconnect structure 124 may be formed of stacked metal layers. In some embodiments, the second interconnect structure 124 is formed from bottom to top, wherein such process is similar to the formation of the first interconnect structure 114. For example, the metal layers 131, 133, 135 and 137 are formed over one another along with corresponding intervening conductive via layers 132, 134 and 136. The IMD 123 is filled among the aforesaid metal layers in order to complete the second interconnect structure 124. A portion of the metal layer 131 is exposed from the first interconnect structure 114.

Referring to FIG. 2F, several bond pads 152 are formed at a topmost level of the second interconnect structure 124. In some embodiments, each of the bond pads 152 has a top surface 152A higher than a top surface 123A of the IMD 123. In some embodiments (not shown), the top surface 123A may be configured to level with the top surface 152A such that the first interconnect structure 124 has a planarized top surface 124A of FIG. 1A. The second semiconductive substrate 122 and the second interconnect structure 124 constitutes the first semiconductor device 120.

The first semiconductor device 110 is flipped and bonded with the semiconductor device 120 as shown in FIG. 2G. The bond pads 154 are electrically bonded with corresponding bond pads 152.

Referring to FIG. 2H, the first semiconductive substrate 112 is thinned down. The thinned semiconductive substrate 112 is thinned to a thickness L measured from a bottom surface 1120 to the top surface 112A. In some embodiments, the thickness L is from about 20 um to about 500 um. In some embodiments, the thickness L is from about 20 um to about 300 um. In some embodiments, the thickness L is from about 40 um to about 120 um.

In FIG. 2I, the dielectric 164 is formed over the first semiconductor device 110. In sonic embodiments, the dielectric 164 may be configured as a passivation layer. In some embodiments, the dielectric 164 includes silicon oxide or silicon nitride. The dielectric 164 may be formed by a deposition operation, such as hot filament CVD, rf-CVD, laser CVD (LCVD), conformal diamond coating processes, MOCVD, thermal evaporation PVD, HDPCVD, LPCVD and the like.

In FIG. 2J, the first via 160 is formed in the first semiconductor substrate 112. The first via 160 may be formed by deposition of a mask layer. The mask layer can be a photoresist mask or hard mask, such as nitride. Then, an etching operation is performed with the mask layer in place. The first via 160 is formed by a suitable etching process, such as a dry etch operation. In some embodiments, the dry etch in the present operation includes a reactive ion etch (RIE) adopting fluorine-containing gases. The mask layer is removed after the first via 160 is completed.

In FIG. 2K, a dielectric material 167 is conformally formed over the first semiconductive substrate 112. In some embodiments, the dielectric material 167 is a different material from that of the dielectric 164. In some embodiments, the dielectric 167 is formed over the dielectric 164, and the sidewalls and bottom surface of the first via 160. The dielectric 167 may be formed by a suitable deposition process, such as a CVD or PVD operation.

In FIG. 2L, a dielectric material 182 is blanket deposited over the dielectric 167. The dielectric material 182 fills the first via 160. In some embodiments, the dielectric material 182 is different from that of the dielectric 167. In some embodiments, the dielectric material 182 is different from that of the dielectric 164.

In FIG. 2M, a removal operation is performed to remove excessive materials above the dielectric layer 164. After the removal operation, a portion of the dielectric layer 167 is left on the sidewalls and bottom surface of the first via 160. As a result, the dielectric 166 is formed in the first via 160. Also, the dielectric 164 is exposed by the removal operation. In some embodiments, the removal operation may be performed by a suitable process, such as a chemical mechanical polishing (CMP) operation. In some embodiments, a portion of the top surface of the filled first via 160, which includes the surfaces 166A and 167A, may include a curve surface due to the dishing effect. In some embodiments, the top surface of the first via 160 may include a concave shape, such as an upwardly concave shape. Therefore, the dielectric 166 may include a top surface 166A with a curved shape. For example, the top surface 166A may include an upwardly concave shape. In some embodiments, the dielectric 167 may include a top surface 166A with a curved shape. For example, the top surface 167A may include an upwardly concave shape.

In FIG. 2N, the second via 160′ is formed in the dielectric 166. The second via 160′ is extended downward and exposes the metal layer 141. The second via 160′ may be formed by deposition of a mask layer. Then, an etching operation is performed with the mask layer in place. The second via 160′ is formed by a suitable etching process, such as a dry etch operation. In some embodiments, the dry etch in the present operation includes a reactive ion etch (RIE) adopting fluorine-containing gases. The mask layer is removed after the second via 160′ is completed.

Referring to FIG. 2O, the first layer 169 is formed in the second via 160′. The first layer 169 may be formed by a by a variety of techniques, e.g., electroplating, electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, PVD, CVD, LPCVD, plasma-enhanced chemical vapor deposition (PECVD), and the like.

Referring to FIG. 2P, the second layer 170 is formed over the second via 160′. Also, the second layer 170 is formed on the first layer 169. The second layer 170 may be formed by a by a variety of techniques, e.g., electroplating, electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, PVD, CVD, LPCVD, plasma-enhanced chemical vapor deposition (PECVD), and the like.

Referring to FIG. 2Q, the UBM 174 is formed over the first via 160. In some embodiments, the UBM 174 covers a portion of the dielectric 164. Then, the connector 172 is formed over the UBM 174.

In view of the foregoing, the present disclosure provides a semiconductor structure in which an improved bond pad is proposed for enhancing structural resistance to foreign stress. The bond pad may comprise at least two layers of conductive materials. The bond pad is disposed in a via. Among the two layers of the bond pad, a first layer comprises a conductive material, such as nickel. Also, the second layer comprises a conductive material, such as gold. In addition, the second layer comprises a cap portion covering the via. Thus, the bond pad exhibits greater stress resistance. The risk of structure cracking or peeling is alleviated accordingly.

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

The present disclosure provides a semiconductor structure comprising a first semiconductor device and a second semiconductor device. The first semiconductor device comprises a first semiconductive substrate, a first interconnect structure over the first semiconductive substrate, a terminal in the first semiconductive substrate where the terminal is configured to electrically couple the first interconnect structure with a connector over the first semiconductive substrate, and a dielectric surrounding the terminal. The second semiconductor device comprises a second semiconductive substrate. The second semiconductor device also comprises a second interconnect over the second semiconductive substrate and configured to bond with the first interconnect structure. The terminal comprises a first layer connected to the second interconnect structure and a second layer extending over the dielectric.

The present disclosure provides a method of manufacturing a semiconductor structure. The method comprises: providing a first semiconductive substrate; forming a first interconnect structure over the first semiconductive substrate; providing a second semiconductive substrate; forming a second interconnect structure over the first semiconductive substrate; bonding the first interconnect structure with the second interconnect structure; forming a first via in the first semiconductive substrate, the via exposing a portion of a top surface of a metal layer in the first interconnect structure; depositing a dielectric in the first via; forming a second via in the dielectric; depositing a first conductive layer in the second via; and depositing a second conductive layer over the first conductive layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method of manufacturing a semiconductor structure, comprising: providing a first semiconductive substrate; forming a first interconnect structure over the first semiconductive substrate; forming a first via in the first semiconductive substrate, the first via exposing a portion of a top surface of a metal layer in the first interconnect structure; depositing a dielectric filling in the first via; etching the dielectric filling in the first via to form a second via having a first dielectric sidewall and a second dielectric sidewall opposing the first dielectric sidewall; depositing a first conductive layer in the second via, wherein the first conductive layer fills the second via extending from the first dielectric sidewall to the second dielectric sidewall and extends to a first height; and depositing a second conductive layer over the first conductive layer, wherein the second conductive layer extends from the first dielectric sidewall to the second dielectric sidewall; a ratio of Young's modulus between the first conductive layer and the second conductive layer is about 1.5 to about 3.5.
 2. The method of claim 1, wherein a portion of the second conductive layer covers a portion of a top surface of the dielectric.
 3. The method of claim 1, wherein the depositing the dielectric filling the first via includes forming a top surface of the dielectric filling the first via into a concave shape.
 4. A method of fabricating a semiconductor structure, comprising: providing a first semiconductive substrate; forming a first interconnect structure over a first surface of the first semiconductive substrate; forming a dielectric layer over the second surface of first semiconductive substrate, the second surface being opposite to the first surface; etching a first via through the dielectric layer and through first semiconductive substrate; filling the first via with one or more dielectric materials, wherein the filling the first via includes disposing the one or more dielectric materials extending between sidewalls of the first via; performing a chemical mechanical polish (CMP) on the one or more dielectric materials to form a dielectric filled trench; after the performing the CMP, etching a second via in the dielectric filled trench; filling the second via with a conductive material; and forming a bond pad over the via with the conductive material and electrically connected to the via with the conductive material.
 5. The method of claim 4, wherein the performing the CMP provides for a curved top surface of the at least one dielectric materials filling the via.
 6. The method of claim 4, wherein the filling the second via includes electroplating.
 7. The method of claim 4, wherein the forming the bond pad includes forming a first metal layer directly on the conductive material.
 8. The method of claim 7, wherein the forming the bond pad includes forming an under bump metallization over the first metal layer.
 9. The method of claim 7, wherein the forming the bond pad includes forming the first metal layer directly on a curved top surface of the conductive material.
 10. The method of claim 4, wherein the filling the first via with one or more dielectric materials includes depositing a first dielectric layer over sidewalls and a bottom surface of the first via and depositing a second dielectric layer, different in composition than the first dielectric layer, such that the second dielectric layer fills a remaining portion of the first via.
 11. The method of claim 4, wherein the forming the bond pad comprises depositing a conductive material with Young's modulus from about 180 GPa to about 220 GPa.
 12. The method of claim 4, wherein the forming the bond pad comprises depositing a first metal layer of nickel, an under bump metallization layer of gold, and a solder bump.
 13. The method of claim 12, wherein the nickel is deposited with a height from about 20,000 Å to about 25,000 Å.
 14. The method of claim 4, wherein the forming the bond pad includes forming a first metal layer directly on the conductive material and directly on at least one of the one or more dielectric materials.
 15. The method of claim 13, wherein the first metal layer a top surface and a bottom surface, and the top surface comprises a first width larger than a second width of the bottom surface.
 16. A method of fabricating a semiconductor structure, comprising: providing a first semiconductive substrate; forming a first interconnect structure over the first semiconductive substrate; providing a second semiconductive substrate having a second interconnect structure formed thereon, wherein the second semiconductive substrate is bonded to the first semiconductive substrate; etching a first via through the second semiconductive substrate, filling the first via with one or more dielectric materials providing a dielectric filled trench; etching a second via in the dielectric filled trench; filling at least a bottom portion of the second via with a first conductive material extending from a first sidewall of the second via to a second sidewall of the second via; forming a second conductive material over the first conductive material, wherein the second conductive material fills an upper portion of the second via extending from the first sidewall of the second via to the second sidewall of the second via and wherein the first and second conductive materials in the second via define a conductive via, wherein the second conductive material extends over a top surface of a remaining portion of the dielectric filled trench on each of a first and second side of the conductive via; forming an under bump metallization (UBM) layer over the first metal layer; and forming a connector over the UBM layer.
 17. The method of claim 16, further comprising: performing a chemical mechanical polish process after filling the first via with one or more dielectric materials and prior to etching the second via.
 18. The method of claim 17, wherein the CMP process forms a concave top surface of the dielectric filled trench. 